Exemplary embodiments relate to a semiconductor memory device and a method of programming the same and, more particularly, to a program method applicable to nonvolatile memory devices.
A nonvolatile memory device, which is a kind of semiconductor memory devices, is characterized in that data stored therein is not erased even though the supply of power is stopped. Data is stored in the memory cells of a nonvolatile memory device by a program operation. The threshold voltages of the memory cells may be shifted by the program operation. The levels of threshold voltages of the memory cells are shifted according to data stored in each memory cell. A program method of storing data of two bits or more in one memory cell has been used.
In a case where data of two bits are stored in one memory cell, a shifted level of the threshold voltage is changed according to the stored data by the program operation. For example, in a case where data ‘11’ is inputted, the threshold voltage of a memory cell may be maintained at a first level of an erase state lower than 0 V. In a case where data ‘10’ is inputted, the threshold voltage of the memory cell may rise up to a second level higher than 0 V. In a case where data ‘00’ is inputted, the threshold voltage of the memory cell may rise up to a third level higher than the second level. In a case where data ‘01’ is inputted, the threshold voltage of the memory cell may rise up to the third level higher than the second level.
Meanwhile, all the threshold voltages of memory cells do not rise up to a target level precisely. Some threshold voltages may rise higher than the target level. For this reason, although the same data is stored in memory cells, threshold voltages of the memory cells are slightly different from one another and distributed within a certain range.
If a distribution of the threshold voltages of memory cells is widened in each level, it is difficult to distinguish the levels of the threshold voltages from one another. In this case, data stored in the memory cells may not be accurately read.
For this reason, in order to narrow a distribution width of the threshold voltages of memory cells, an incremental step pulse programming (ISPP) method has been proposed. The ISPP method is well known, and a detailed description thereof is omitted.
Meanwhile, with a reduction in the size of a memory cell, interference between the memory cells becomes intensified. Although the memory cells are programmed according to the ISPP method, it becomes difficult to narrow a distribution width of threshold voltages of the memory cells to a desired range. For this reason, a double verification operation using two verification voltages for each level in a verification operation for detecting the levels of threshold voltages of memory cells has been proposed.
More particularly, when selected memory cells are programmed in order to raise their threshold voltages from a first level to a second level, after programming the selected memory cells the threshold voltages of the selected memory cells are detected twice by using a target verification voltage (i.e., corresponding to the second level) and a temporary verification voltage lower than the target verification voltage. As a result of the detection, the selected memory cells may be classified into first memory cells each having a threshold voltage lower than the temporary verification voltage, second memory cells each having a threshold voltage higher than the temporary verification voltage and lower than the target verification voltage, and third memory cells each having a threshold voltage higher than the target verification voltage. If the first and second memory cells each having a threshold voltage lower than the target verification voltage are detected, the first and second memory cells are programmed again by using a program voltage higher than a program voltage used previously.
Meanwhile, when programming the first and second memory cells again, 0 V is supplied to bit lines coupled to the first memory cells, and a voltage higher than 0 V and lower than a power source voltage Vcc is supplied to bit lines coupled to the second memory cells. In this case, an increment of the threshold voltages of the second memory cells is lees in comparison to the first memory cells and can be prevented from rising higher than the target verification voltage. Consequently, the selected memory cells can be programmed so that the threshold voltages of the selected memory cells are distributed within a narrow range.
In the case of the double verification operation, two verification voltages are to be used for each verification operation. Accordingly, if memory cells are programmed according to the ISPP method using the double verification operation, the program time may be increased.